eglantine-cirakg/src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp, branch nx2 Mirror of github.com/cira0100/Eglantine-public nx2, a fork of Djihads80/Eglantine. https://git.cirakg.xyz/eglantine-cirakg/atom?h=nx2 2025-11-03T19:20:19+00:00 [shader_recompiler] Add IAbs64 to prevent errors when using I2F with a 64-bit packed CBUF variant (#2918) 2025-11-03T19:20:19+00:00 lizzie lizzie@eden-emu.dev 2025-11-03T19:20:19+00:00 urn:sha1:0e6ea2d9d66bc7bd4019ab10324e75e73e96f517 - Using I2F cbuf variant (packed 32x2 aka. U64) - Code will call IAbs() if some conditions are met (signed + abs bit) - Uh oh we don't have a variant for 64 bits! - Fuck now we just made BAD ir code :( Signed-off-by: lizzie <lizzie@eden-emu.dev> Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/2918 Reviewed-by: MaranBr <maranbr@eden-emu.dev> Reviewed-by: Caio Oliveira <caiooliveirafarias0@gmail.com> Co-authored-by: lizzie <lizzie@eden-emu.dev> Co-committed-by: lizzie <lizzie@eden-emu.dev> general: Convert source file copyright comments over to SPDX 2022-04-23T09:55:32+00:00 Morph 39850852+Morph1984@users.noreply.github.com 2022-04-23T08:59:50+00:00 urn:sha1:2b87305d319f0bd04da36fb96314934f37b12637 This formats all copyright comments according to SPDX formatting guidelines. Additionally, this resolves the remaining GPLv2 only licensed files by relicensing them to GPLv2.0-or-later. shader_recompiler: Adjust emit_context includes 2021-12-05T23:11:19+00:00 ameerj 52414509+ameerj@users.noreply.github.com 2021-12-05T21:42:03+00:00 urn:sha1:efd428c747d18c0582ef75dba58a000aeed8d214 shader: Add integer division opcodes 2021-11-16T21:11:28+00:00 ReinUsesLisp reinuseslisp@airmail.cc 2021-07-26T00:27:21+00:00 urn:sha1:8cfa8cda165b66603cdce612014e8c334c8c782e opengl: Implement LOP.CC 2021-07-23T01:51:39+00:00 ameerj 52414509+ameerj@users.noreply.github.com 2021-06-25T17:09:45+00:00 urn:sha1:33d21ac2db1d4e35ec6245a274d7c4bcc2028986 Used by MH:Rise shader: Remove IAbs64 2021-07-23T01:51:39+00:00 ReinUsesLisp reinuseslisp@airmail.cc 2021-06-22T21:28:21+00:00 urn:sha1:f158fe9359bec302cb0c6c497e5fda2b5bd709f1 glasm: Fix INeg32 on negative immediates 2021-07-23T01:51:33+00:00 ReinUsesLisp reinuseslisp@airmail.cc 2021-05-25T05:48:03+00:00 urn:sha1:8d77a943cc131efdb8bc7b25633dee202945a754 glasm: Catch more register leaks 2021-07-23T01:51:33+00:00 ReinUsesLisp reinuseslisp@airmail.cc 2021-05-25T05:22:21+00:00 urn:sha1:143db4b112ce2fad78b86ab95f11cb301887b226 Add support for null registers. These are used when an instruction has no usages. This comes handy when an instruction is only used for its CC value, with the caveat of having to invalidate all pseudo-instructions before defining the instruction itself in the register allocator. This commits changes this. Workaround a bug on Nvidia's condition codes conditional execution using branches. glasm: Implement int64 add and subtract 2021-07-23T01:51:33+00:00 ReinUsesLisp reinuseslisp@airmail.cc 2021-05-23T23:16:09+00:00 urn:sha1:46edc93371eab221ab73f427447edd1398983b27 glasm: Implement 64-bit shifts 2021-07-23T01:51:32+00:00 ReinUsesLisp reinuseslisp@airmail.cc 2021-05-19T20:09:29+00:00 urn:sha1:d95e33ac44ecaaa9df388339a84dce4b2c256a6d