eglantine-cirakg/src/video_core/shader_cache.cpp, branch nx2

shader_cache: use sorted membership for large removal batches

2026-11-02T18:58:55+00:00

Keep the linear path for sixteen or fewer removals. For larger batches, sort the auxiliary pointer list and binary-search it while preserving storage order and the same invalidation decisions. Existing real-cache differential tests cover both paths. Assisted-by: Codex (implementation, review, commit text and automated validation) (cherry picked from commit 7e2c8a535230d9810db07706d79130ce0f1b88f1)

shader_cache: batch memory-write invalidations without skipping ranges

2026-11-02T18:58:54+00:00

Adapt the batching from ymatrix1/Eglantine PR #237, retaining all CPU invalidations. Acquire the lock once and remove pending shaders once per write batch. Compare real cache contents with sequential invalidation across randomized overlapping writes and pending removals. Assisted-by: Codex (implementation, review, commit text and automated validation) (cherry picked from commit b65f818d7789ffadfb58fe4543b18060fd88ce53)

nx2: capture and lower native shader programs once

2026-11-01T23:11:25+00:00

Native programs were captured and lowered when their ShaderInfo was made and again for every environment built for their pipelines. The ShaderInfo now keeps the lowered code and the environments adopt it. Capture also reads a 4 KiB page at a time instead of flushing caches per instruction, and cached native programs fold bank 1 reads like live ones. Ported from Wael3rd/Eglantine-MKW (0ae093058e, 65a6aa877a, df076133c4). Assisted-by: Claude Sonnet 5.5 (porting the fixes) (cherry picked from commit 3af11ac401ad3061c183281d8c98c16c1d6da456)

video_core: draw Switch 2 task/mesh pipelines with VK_EXT_mesh_shader

2026-11-01T16:29:30+00:00

While SET_MESH_CONTROL is on, a native draw binds a task program in the vertex slot, its mesh program in the tessellation slot and a header-only pass-through geometry program naming the per-primitive outputs. Translate the first two as task and mesh programs with the mesh registers (SET_MESH_SHADER_A/B, SET_MESH_INIT_SHADER) and that header, key their pipelines by them, and build pipelines with task/mesh stages and no vertex input, input assembly or tessellation state. The draw's vertex count is the number of task workgroups: record vkCmdDrawMeshTasksEXT. Enable VK_EXT_mesh_shader (task and mesh only) when the host has it; draws are skipped without it, as they were before.

nx2: memo for compute macros; one lock per inline upload; cheaper shader invalidation

2026-10-29T04:45:20+00:00

- Compute engine macros replay repeated calls like 3D ones (title 1's compute macro path fell from ~27% to ~14% of the GPU thread). - AccelerateInlineToMemory takes the buffer and texture cache mutexes together instead of one after the other. - ShaderCache::InvalidatePagesInRegion looks at the rejected programs only when the write can reach one (bounds kept as they are added); it ran a locked scan for every inline upload and pre-draw invalidation. Inline uploads went from ~10% to ~4% of the GPU thread.

nx2: measure the TSC on AMD, no rethrows for rejected shaders, debug hooks off the hot path

2026-10-29T03:07:49+00:00

- AMD CPUs have no CPUID leaf 0x15, so the TSC frequency stayed 0 and every guest CNTPCT read went through QueryPerformanceCounter (~10% of the game's main core in title 1). Measure it like Intel CPUs without a crystal frequency. - A rejected native shader was rethrown (two C++ throws) every time it was bound; return false instead (~1-2% of the GPU thread). - The semaphore watch, pushbuffer entry hashing, first-write trace and per-macro debug logs ran on every command word or macro call; they now cost a flag check unless their environment variable is set (~4% of the GPU thread). Also starts the macro engine's profile zone.

Jump-table programs end at their self-branch; aligned wide zero stores

2026-10-28T18:50:32+00:00

- With a BRX the jump targets live in a constant buffer, so capture and lowering keep going past EXITs to the compiler's closing branch-to-self (a title 1 compute program jumped to 0xae0, just past the first EXIT). - 128-bit stores of RZ use R248-R251 (Eden wants 4-aligned data registers). - The rejected-program cache covers environment construction, where native programs are lowered (it never applied before), and logs the stage slot. Title 1 reaches its title screen with the ground drawn.

IMAD.SHL as a shift; EDEN_NX2_REJECT; log where rejected programs are bound

2026-10-28T18:44:18+00:00

- IMAD by a power of two lowers to SHL imm, the form Eden's jump-table tracking expects (a title 1 compute program failed "track indirect branch"). - EDEN_NX2_REJECT=: treat those native programs as rejected, to bisect a behaviour change without rebuilding. - A rejected graphics program logs its stage slot, header and slot registers once (for the task/mesh pipeline setup). - Notes: rows 87-92, title 1 status.

Cache rejected native shaders and log each rejection once

2026-10-28T18:31:00+00:00

A rejected program was lowered again (and logged) on every draw or dispatch: 1.7M log lines in 13 minutes of title 1. The shader cache keeps the first exception per address until guest memory there is written, and the error logs are deduplicated.

nx2: lower every shader title 4 uses in game

2026-10-28T05:18:23+00:00

- Tensor-core ops for its neural compute pass: HMMA.16816.F16 (SHFL + HFMA2), MOVM.16.MT88 and LDSM .MT88. Opt-in via EDEN_NX2_TENSOR: the expansion (372 HMMAs) takes the host driver minutes to compile. - HSETP2 with an immediate half pair; skip @!PT instructions. - Constant bank 24, read only by three NVN2 fullscreen vertex shaders and never bound by the game, reads from bank 17 (also never bound: zeros, as on hw). - Debug dumps of the vertex stage's bound constant buffers on rejection. All 214 shaders captured after the menu lower (213 without EDEN_NX2_TENSOR).