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<title>eglantine-cirakg/src/video_core/texture_cache/util.cpp, branch nx2</title>
<subtitle>Mirror of github.com/cira0100/Eglantine-public nx2, a fork of Djihads80/Eglantine.</subtitle>
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<updated>2026-11-01T16:29:56+00:00</updated>
<entry>
<title>texture_cache: back large sparse 2D images by sparse block</title>
<updated>2026-11-01T16:29:56+00:00</updated>
<author>
<name>Takoroka</name>
<email>137927095+Takoroka@users.noreply.github.com</email>
</author>
<published>2026-11-01T04:36:38+00:00</published>
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<content type='text'>
Mario Kart World's nine world-sized masks (R8 16384x16384, RG16 and
R16 8192x8192, 170-341 MB each) live in sparse regions the game maps
its own memory into, a few MiB of each. Since a mapped tile counts as
written, the texture cache backed and uploaded each mask in full: about
2.9 GB of device memory, and a whole-mask upload for every tile the
game streamed in.

Such images (single layer, one texel per block, colour, in a sparse
region, 32 MiB or more) are now unbacked SparseTiles images. The
texture cache records the guest ranges written to them; Image::BindTiles
gives the host sparse blocks under those ranges memory, and only those
rectangles are unswizzled, a row of whole GOB blocks at a time, and
uploaded. A new image starts with the tiles the game maps there (nx2:gpu
216 now records them per 64 KiB), or the written blocks where it maps
none. Unmapped tiles keep their blocks and are loaded as zeros.

Checked against the full unswizzle on 400 ordinary game images (row
padding, mip chains, odd sizes): no row differs. Not on AMD drivers,
which cannot sample images with unbound memory.

Mario Kart World title screen, 150 s, against backing the masks whole:
dedicated VRAM 6.6 -&gt; 6.2 GB, shared 1.0 -&gt; 0.3 GB, peak 8.2 -&gt; 6.9 GB.
</content>
</entry>
<entry>
<title>1st pass of review: code cleanup &amp; windows test</title>
<updated>2026-10-31T17:04:23+00:00</updated>
<author>
<name>néo Luigi</name>
<email>85024393+neoluigi4123@users.noreply.github.com</email>
</author>
<published>2026-10-31T14:33:09+00:00</published>
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<id>urn:sha1:82963e6750cef756d2ad4d1115dc9dca420d4313</id>
<content type='text'>
Assisted-by: Claude Opus 5.5 (review, cleanup and log analysis)
</content>
</entry>
<entry>
<title>ASTC: decode and re-compress to BC1/BC3 on the GPU; texture cache budget</title>
<updated>2026-10-29T00:43:01+00:00</updated>
<author>
<name>Takoroka</name>
<email>137927095+Takoroka@users.noreply.github.com</email>
</author>
<published>2026-10-29T00:43:01+00:00</published>
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<id>urn:sha1:0d5534a2883329183ae8aa89b3fe1c7b67291ece</id>
<content type='text'>
- accelerate_astc=Gpu with astc_recompression=Bc1/Bc3 now decodes ASTC
  with the GPU decoder into a temporary RGBA8 image (dedicated memory,
  freed once the GPU is past it) and compresses it with a new compute
  shader (bc_encoder.comp: bounding-box endpoints along the colours'
  covariance, inset 1/16, nearest palette entry; BC3 alpha ramp; BC1
  punch-through), then copies the blocks into the image. No CPU decode,
  so streamed textures are ready the frame they are first used instead
  of showing placeholders for seconds; the decode pass no longer waits
  for the GPU on this path.
- The CPU path (CpuAsynchronous) fills a new image with zero blocks
  before its first decode instead of showing stale VRAM, and the
  transcode pool is a quarter of the hardware threads.
- Switch 2 titles: collector thresholds near the device budget, re-read
  every 60 frames from VK_EXT_memory_budget (another game shrank it from
  7.0 to 5.4 GB).
- EDEN_NX2_HIDE_WINDOW=0 now leaves the window visible.
</content>
</entry>
<entry>
<title>Texture cache: stop the churn, the per-frame image leak and garbage textures</title>
<updated>2026-10-28T23:32:48+00:00</updated>
<author>
<name>Takoroka</name>
<email>137927095+Takoroka@users.noreply.github.com</email>
</author>
<published>2026-10-28T23:32:48+00:00</published>
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- Unmapped GPU addresses get a stand-in CPU address fixed by the GPU
  address. A fresh one per lookup meant FindImage never found an image
  there again: title 1's bloom chain at 0xf0000-0x15b600 was re-created
  on every use (~5,400 images per 600 frames), filling VRAM.
- ASTC whose blocks carry no alpha (exact endpoint-mode scan reusing the
  decoder's block parsing) is re-compressed to BC1 instead of BC3, half
  the size; about 70% of title 1's ASTC qualifies. Copies between BC1
  and BC3 hosts are skipped (their guest data is uploaded instead).
  EDEN_NX2_ASTC_BC1=0 turns it off.
- Deleting an image cancels every decode still queued for it. An image
  re-decoded mid-decode has two; the first to finish cleared IsDecoding,
  the second was not cancelled and was uploaded into the next image to
  take the slot: garbage textures (the title logo, road patches) and a
  staging overrun when that image was smaller.
- Diagnostics: images created and deleted per 600 frames by shape,
  collector deletions, async decodes, BC1/BC3 split; collector
  thresholds overridable (EDEN_NX2_TC_EXPECTED_MIB/CRITICAL_MIB); GPU
  ASTC decode wait timing (EDEN_NX2_ASTC_FLUSH=1 submits without it).

Title 1 attract loop: device memory 4.8-5.1 GB instead of 5.9-6.1 GB, no
decoded textures evicted, ~17 -&gt; 22-23 fps.
</content>
</entry>
<entry>
<title>Keep huge ASTC arrays from a lower mip on the host (title 1 terrain)</title>
<updated>2026-10-28T19:37:34+00:00</updated>
<author>
<name>Takoroka</name>
<email>137927095+Takoroka@users.noreply.github.com</email>
</author>
<published>2026-10-28T19:37:34+00:00</published>
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<id>urn:sha1:934ad3b97c12e1d40cf4e1f6094c756873b6af82</id>
<content type='text'>
Title 1's terrain virtual textures are 8192x8192x68 ASTC 8x8 sRGB arrays with
12 levels: 1.5 GB in guest memory (fully backed) but 23 GB each as the RGBA8
Eden decodes ASTC to, so they were created unbacked and the near terrain
sampled black. A GPU-decoded ASTC 2D array over 1 GiB decoded now keeps only
the levels from the first one that fits in 512 MiB (here 3: 1024x1024, 380
MiB); host mip 0 is that guest level. Uploads read each layer's tail of the
mip chain into a compact buffer and decode only those levels, views shift
their level range, and these images are never downloaded. Normalized
coordinates and derivative LOD address the smaller image correctly; the
nearest terrain is lower resolution than on the console.

Also logs how unbacked images are used (views, render targets, blits, DMA).
</content>
</entry>
<entry>
<title>Switch 2: Turing macros, native compute, Ampere shader lowering, native tiling</title>
<updated>2026-10-28T02:26:16+00:00</updated>
<author>
<name>Takoroka</name>
<email>137927095+Takoroka@users.noreply.github.com</email>
</author>
<published>2026-10-28T02:26:16+00:00</published>
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<id>urn:sha1:51207c73c889dbdc4a586a5da23314f6d33e4eb9</id>
<content type='text'>
From changes.patch: the TU104/GA10x MME interpreter (shared macro context for
the process's channels, also on the compute class), native compute with QMD
3.0 dependency scheduling, the Ampere-to-Maxwell shader lowering, native
vertex stream sizes, and the console's GOB swizzle for textures, DMA copies
and the host unswizzle shaders. Switch 2 channels turn all of it on at init.

The lowering is widened for title 4 (all 32 of its programs lower): general
TEX (any dimension/LOD/mask, operand split 1+1/2+1/2+2/4+n, any but consistent
descriptor buffer), cube/array, SULD channel masks, 128-bit STG, indexed IPA,
VOTE, SHFL with any immediate or predicate output, R2P/P2R byte select,
uniform ULOP3/ULEA/UBREV/UFLO.SH/UISETP signed/UMOV URZ, IMNMX cbuf, IADD3
and FFMA uniform operands, FMUL /4 /8 x8, and BSSY/BSYNC/BREAK/WARPSYNC as
no-ops. The capture stops at unmapped memory. EDEN_NX2_SHADER_DUMP dumps every
native program; tools in C:\dev\nx2work test the lowering offline.
</content>
</entry>
<entry>
<title>[video_core] Increase MAX_MIP_LEVELS to 16 according to specs (#2965)</title>
<updated>2025-11-07T00:42:52+00:00</updated>
<author>
<name>MaranBr</name>
<email>maranbr@outlook.com</email>
</author>
<published>2025-11-07T00:42:52+00:00</published>
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<id>urn:sha1:569dbfe8c04e5f852ef4db17f5f219fe2da27228</id>
<content type='text'>
This increases MAX_MIP_LEVELS from 14 to 16, according to specs.

Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/2965
Reviewed-by: Maufeat &lt;sahyno1996@gmail.com&gt;
Co-authored-by: MaranBr &lt;maranbr@outlook.com&gt;
Co-committed-by: MaranBr &lt;maranbr@outlook.com&gt;
</content>
</entry>
<entry>
<title>[video_core] Bypass mip level assertion to ASSERT_MSG (#2914)</title>
<updated>2025-11-01T00:36:03+00:00</updated>
<author>
<name>JPikachu</name>
<email>jpikachu@eden-emu.dev</email>
</author>
<published>2025-11-01T00:36:03+00:00</published>
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<content type='text'>
This will bypass the check and continue execution,
preventing crashes in cases where games (like CTGP-DX) may request
more mip levels than supported. This is a temporary solution to bypass
instead of ending the crashing when asserts fail.

Co-authored-by: MaranBr &lt;maranbr@outlook.com&gt;

Co-authored-by: JPikachu &lt;jpikachu.eden@gmail.com&gt;
Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/2914
Reviewed-by: MaranBr &lt;maranbr@eden-emu.dev&gt;
Reviewed-by: Caio Oliveira &lt;caiooliveirafarias0@gmail.com&gt;
Co-authored-by: JPikachu &lt;jpikachu@eden-emu.dev&gt;
Co-committed-by: JPikachu &lt;jpikachu@eden-emu.dev&gt;
</content>
</entry>
<entry>
<title>[cmake] enable clang-cl and WoA builds (#348)</title>
<updated>2025-09-09T18:47:49+00:00</updated>
<author>
<name>lizzie</name>
<email>lizzie@eden-emu.dev</email>
</author>
<published>2025-09-09T18:47:49+00:00</published>
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<id>urn:sha1:9d2681ecc9565681db623fb71799e76381998512</id>
<content type='text'>
Compilation and CMake fixes for both Windows on ARM and clang-cl, meaning Windows can now be built on both MSVC and clang on both amd64 and aarch64.

Compiling on clang is *dramatically* faster so this should be useful for CI.

Co-authored-by: crueter &lt;crueter@eden-emu.dev&gt;
Co-authored-by: crueter &lt;crueter@crueter.xyz&gt;
Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/348
Reviewed-by: CamilleLaVey &lt;camillelavey99@gmail.com&gt;
Reviewed-by: crueter &lt;crueter@eden-emu.dev&gt;
Co-authored-by: lizzie &lt;lizzie@eden-emu.dev&gt;
Co-committed-by: lizzie &lt;lizzie@eden-emu.dev&gt;
</content>
</entry>
<entry>
<title>[texture_cache] Enforce conservative 3D texture aliasing. Consistently merge/lookup images. (#196)</title>
<updated>2025-08-04T16:39:17+00:00</updated>
<author>
<name>weakboson</name>
<email>weakboson@quantum-field.net</email>
</author>
<published>2025-08-04T16:39:17+00:00</published>
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<id>urn:sha1:33275c28d34589e0e1cf639a47187d9ce4f9e34f</id>
<content type='text'>
Previously, the merging strategy is permissive but the lookup strategy is strict. Together they create a infinite merge loop because lookup always fails and merges are always executed.
The last attempt to fix this issue made the lookup strategy more permissive which created unexpected aliased textures.
This commit implements an alternative: make the merging strategy strict.

Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/196
Reviewed-by: Shinmegumi &lt;shinmegumi@eden-emu.dev&gt;
Co-authored-by: weakboson &lt;weakboson@quantum-field.net&gt;
Co-committed-by: weakboson &lt;weakboson@quantum-field.net&gt;
</content>
</entry>
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