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authorTakoroka <137927095+Takoroka@users.noreply.github.com>2026-11-01 13:25:59 -0500
committerTakoroka <137927095+Takoroka@users.noreply.github.com>2026-11-01 13:25:59 -0500
commit31e4a803d686f7922fcae9de7db5bebcfe368e46 (patch)
tree185e54713be11f9bf2b45c0a4631cad24b822485
parentfdc36daf714ee8135d927a832e48e8be7932bb91 (diff)
parentdd8742e5634d8e3f81c84f869cd210037f366731 (diff)
Merge remote-tracking branch 'origin/fix/nx2-gpu-engine-support-flags' into test/linux-all-prs
-rw-r--r--src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp b/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp
index 5998940afa..69c0313228 100644
--- a/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp
+++ b/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp
@@ -218,6 +218,10 @@ void ApplyNx2Characteristics(GC& gc) {
if (remap) {
gc.flags |= 1ULL << 35;
}
+ // Engine support bits 40-44 (2D, 3D, compute, inline-to-memory, ZBC). NvRm's newer device
+ // path lists a class family in the device info only when its bit is set; without them a
+ // device opened that way has no compute class and Fire Emblem's CUDA driver reports no device.
+ gc.flags |= 0x1FULL << 40;
// The Switch 2 layout keeps nine s16 interface versions at 0x70..0x80 (like nvgpu's
// *_ioctl_nr_last); its NvRm requires e.g. [0x78] >= 6 and enables features above 0xa, 0x1f