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| author | Takoroka <137927095+Takoroka@users.noreply.github.com> | 2026-10-31 08:42:11 -0400 |
|---|---|---|
| committer | Takoroka <137927095+Takoroka@users.noreply.github.com> | 2026-11-01 12:23:53 -0500 |
| commit | dd8742e5634d8e3f81c84f869cd210037f366731 (patch) | |
| tree | 16e3fed2d2b8a1d9882cbc42b6babe9b8ae1e174 /src/common/sparse_large_vector.cpp | |
| parent | 6bde8c20d1f7c020a920e59a989c03822a08445d (diff) | |
nvdrv: report 2D/3D/compute/I2M/ZBC support in Switch 2 GPU flags
Switch 2 NvRm has a second device path that builds the device's class
list from the chip table but adds a class family only when its support
bit is set in the characteristics flags (bits 40-44: 2D, 3D, compute,
inline-to-memory, ZBC). We set none of them, so a device opened that
way had no compute class. Fire Emblem's CUDA driver opens its device
through that path, saw compute class 0 and reported no device; the
cleanup that followed aborted the game (2162-0001).
Diffstat (limited to 'src/common/sparse_large_vector.cpp')
0 files changed, 0 insertions, 0 deletions