diff options
| author | mailwl <mailwl@gmail.com> | 2016-04-06 14:57:43 +0300 |
|---|---|---|
| committer | mailwl <mailwl@gmail.com> | 2016-04-06 19:46:58 +0300 |
| commit | f1fb108e030ed8fb92129769ab00d0c5e2a4227f (patch) | |
| tree | 67e837d30e2a84e725f6492155148163028e0026 /src/core/arm/dyncom/arm_dyncom_interpreter.cpp | |
| parent | 8a86b69dcd140d0a53df79cea79c3ee242aafe37 (diff) | |
Fix thumb ADR instruction alignment
Diffstat (limited to 'src/core/arm/dyncom/arm_dyncom_interpreter.cpp')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index 9ed61947ee..a6faf42b94 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -3955,9 +3955,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { add_inst* const inst_cream = (add_inst*)inst_base->component; - u32 rn_val = RN; - if (inst_cream->Rn == 15) - rn_val += 2 * cpu->GetInstructionSize(); + u32 rn_val = CHECK_READ_REG15_WA(cpu, inst_cream->Rn); bool carry; bool overflow; @@ -6167,9 +6165,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { sub_inst* const inst_cream = (sub_inst*)inst_base->component; - u32 rn_val = RN; - if (inst_cream->Rn == 15) - rn_val += 2 * cpu->GetInstructionSize(); + u32 rn_val = CHECK_READ_REG15_WA(cpu, inst_cream->Rn); bool carry; bool overflow; |