diff options
| author | MrPurple666 <antoniosacramento666usa@gmail.com> | 2025-04-01 04:34:05 -0300 |
|---|---|---|
| committer | MrPurple666 <antoniosacramento666usa@gmail.com> | 2025-04-11 17:04:55 -0300 |
| commit | 27ceda2c6cf01b165bc7517343f4e68a258db7a6 (patch) | |
| tree | 02027fbcae4ef26947f9ac821c15a6c7fd8ad382 /src/core/arm/nce/arm_nce.cpp | |
| parent | 777b674edfe317965018bfb837ce76fee0378667 (diff) | |
WIP: DO-NOT-MERGE: NCE experiments: Fix build errors
Diffstat (limited to 'src/core/arm/nce/arm_nce.cpp')
| -rw-r--r-- | src/core/arm/nce/arm_nce.cpp | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/src/core/arm/nce/arm_nce.cpp b/src/core/arm/nce/arm_nce.cpp index 76b476e672..90891e241d 100644 --- a/src/core/arm/nce/arm_nce.cpp +++ b/src/core/arm/nce/arm_nce.cpp @@ -382,23 +382,23 @@ void ArmNce::SignalInterrupt(Kernel::KThread* thread) { } } -void ArmNce::ClearInstructionCache() { - #if defined(__GNUC__) || defined(__clang__) - const size_t PAGE_SIZE = 4096; - void* start = (void*)((uintptr_t)__builtin_return_address(0) & ~(PAGE_SIZE - 1)); - void* end = (void*)((uintptr_t)start + PAGE_SIZE * 2); // Clear two pages for better coverage - - // Prefetch next likely pages - __builtin_prefetch((void*)((uintptr_t)end), 1, 3); - __builtin___clear_cache(static_cast<char*>(start), static_cast<char*>(end)); - #endif +const std::size_t CACHE_PAGE_SIZE = 4096; - #ifdef __aarch64__ - // Ensure all previous memory operations complete - asm volatile("dmb ish" ::: "memory"); - asm volatile("dsb ish" ::: "memory"); - asm volatile("isb" ::: "memory"); - #endif +void ArmNce::ClearInstructionCache() { +#if defined(__GNUC__) || defined(__clang__) + void* start = (void*)((uintptr_t)__builtin_return_address(0) & ~(CACHE_PAGE_SIZE - 1)); + void* end = + (void*)((uintptr_t)start + CACHE_PAGE_SIZE * 2); // Clear two pages for better coverage + // Prefetch next likely pages + __builtin_prefetch((void*)((uintptr_t)end), 1, 3); + __builtin___clear_cache(static_cast<char*>(start), static_cast<char*>(end)); +#endif +#ifdef __aarch64__ + // Ensure all previous memory operations complete + asm volatile("dmb ish" ::: "memory"); + asm volatile("dsb ish" ::: "memory"); + asm volatile("isb" ::: "memory"); +#endif } void ArmNce::InvalidateCacheRange(u64 addr, std::size_t size) { |