[dynarmic] Fix ISB with new JIT schema (#3576)

If an ISB is issued, the changes on the memory wouldn't be reflected
Now we emulate "instruction cache" properly by just telling the mechanism to re-fetch the entire page again (to make ANY changes visible immediately)

This mainly fixes a potential issue where an ISB is emitted before a branch on the same codepage.

Signed-off-by: lizzie <lizzie@eden-emu.dev>
Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/3576
Reviewed-by: CamilleLaVey <camillelavey99@gmail.com>
Reviewed-by: crueter <crueter@eden-emu.dev>
Reviewed-by: DraVee <dravee@eden-emu.dev>
Co-authored-by: lizzie <lizzie@eden-emu.dev>
Co-committed-by: lizzie <lizzie@eden-emu.dev>

1 files changed, 3 insertions, 0 deletions

diff --git a/src/core/hle/service/jit/jit_context.cpp b/src/core/hle/service/jit/jit_context.cpp
index 327825ee83..a927318a7c 100644
--- a/src/core/hle/service/jit/jit_context.cpp
+++ b/src/core/hle/service/jit/jit_context.cpp
@@ -56,6 +56,9 @@ public:
         }
         return cached_code_page.inst[(vaddr & Core::Memory::YUZU_PAGEMASK) / sizeof(u32)];
     }
+    void InstructionSynchronizationBarrierRaised() override {
+        last_code_addr = 0; //reset back, force refetch
+    }
     u8 MemoryRead8(u64 vaddr) override {
         return ReadMemory<u8>(vaddr);
     }