dynarmic: decode ARMv8.1-8.5 instructions used by Switch 2 code

Switch 2 titles are built for a Cortex-A78C class core. Scanning one title's
.text with dynarmic's own decoder table found ~115k RETAB, ~37k LDAPR,
~25k LSE atomics, ~6.6k CAS, ~2.5k SWP plus a few CASP/XPAC/PAC/STG, none of
which dynarmic decoded (only the declarations existed).

- LSE atomics, SWP, CAS, CASP: exclusive load + op + exclusive store; on
  store failure no register is written and the instruction is retried
  (CheckBit terminal), so it stays atomic across cores.
- LDAPR: ordered load, like LDAR.
- Pointer authentication: identity (nothing is ever signed). RETAA/RETAB,
  BRA*/BLRA*, LDRAA/LDRAB, PAC*/AUT*/XPAC*, PACGA.
- MTE: tags are always 0; STG/ST2G only write back, STZG/STZ2G zero the
  granules, STGP stores the pair, IRG/GMI/ADDG/SUBG ignore tags.

tools/nx2/a64_coverage.py reports which encodings in an NSO's .text the
decoder table does not match.

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