nvdrv: report 2D/3D/compute/I2M/ZBC support in Switch 2 GPU flags

Switch 2 NvRm has a second device path that builds the device's class
list from the chip table but adds a class family only when its support
bit is set in the characteristics flags (bits 40-44: 2D, 3D, compute,
inline-to-memory, ZBC). We set none of them, so a device opened that
way had no compute class. Fire Emblem's CUDA driver opens its device
through that path, saw compute class 0 and reported no device; the
cleanup that followed aborted the game (2162-0001).

1 files changed, 4 insertions, 0 deletions

diff --git a/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp b/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp
index 5998940afa..69c0313228 100644
--- a/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp
+++ b/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp
@@ -218,6 +218,10 @@ void ApplyNx2Characteristics(GC& gc) {
     if (remap) {
         gc.flags |= 1ULL << 35;
     }
+    // Engine support bits 40-44 (2D, 3D, compute, inline-to-memory, ZBC). NvRm's newer device
+    // path lists a class family in the device info only when its bit is set; without them a
+    // device opened that way has no compute class and Fire Emblem's CUDA driver reports no device.
+    gc.flags |= 0x1FULL << 40;
 
     // The Switch 2 layout keeps nine s16 interface versions at 0x70..0x80 (like nvgpu's
     // *_ioctl_nr_last); its NvRm requires e.g. [0x78] >= 6 and enables features above 0xa, 0x1f