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authorFernandoS27 <fsahmkow27@gmail.com>2021-04-10 00:29:12 +0200
committerameerj <52414509+ameerj@users.noreply.github.com>2021-07-22 21:51:27 -0400
commitee8beff1686c0e661696d20647ddde9ce3f787e1 (patch)
tree325133fcabd67f3e21fdb4096b5cc8c59875b7ad /src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_right.cpp
parent99cfd73ba7955f5d209f30d0d2fb1a0b6dfe3dcc (diff)
shader: Implement CC for ISET, FSET, PSET, CSET, and DSET
Throw when other instructions are missing CC.
Diffstat (limited to 'src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_right.cpp')
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_right.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_right.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_right.cpp
index 4025b13589..be00bb605b 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_right.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_right.cpp
@@ -16,12 +16,16 @@ void SHR(TranslatorVisitor& v, u64 insn, const IR::U32& shift) {
BitField<39, 1, u64> is_wrapped;
BitField<40, 1, u64> brev;
BitField<43, 1, u64> xmode;
+ BitField<47, 1, u64> cc;
BitField<48, 1, u64> is_signed;
} const shr{insn};
if (shr.xmode != 0) {
throw NotImplementedException("SHR.XMODE");
}
+ if (shr.cc != 0) {
+ throw NotImplementedException("SHR.CC");
+ }
IR::U32 base{v.X(shr.src_reg_a)};
if (shr.brev == 1) {