Switch 2: Turing macros, native compute, Ampere shader lowering, native tiling

From changes.patch: the TU104/GA10x MME interpreter (shared macro context for
the process's channels, also on the compute class), native compute with QMD
3.0 dependency scheduling, the Ampere-to-Maxwell shader lowering, native
vertex stream sizes, and the console's GOB swizzle for textures, DMA copies
and the host unswizzle shaders. Switch 2 channels turn all of it on at init.

The lowering is widened for title 4 (all 32 of its programs lower): general
TEX (any dimension/LOD/mask, operand split 1+1/2+1/2+2/4+n, any but consistent
descriptor buffer), cube/array, SULD channel masks, 128-bit STG, indexed IPA,
VOTE, SHFL with any immediate or predicate output, R2P/P2R byte select,
uniform ULOP3/ULEA/UBREV/UFLO.SH/UISETP signed/UMOV URZ, IMNMX cbuf, IADD3
and FFMA uniform operands, FMUL /4 /8 x8, and BSSY/BSYNC/BREAK/WARPSYNC as
no-ops. The capture stops at unmapped memory. EDEN_NX2_SHADER_DUMP dumps every
native program; tools in C:\dev\nx2work test the lowering offline.

1 files changed, 20 insertions, 0 deletions

diff --git a/src/video_core/engines/engine_upload.cpp b/src/video_core/engines/engine_upload.cpp
index ba21eec4c4..0ffdae8036 100644
--- a/src/video_core/engines/engine_upload.cpp
+++ b/src/video_core/engines/engine_upload.cpp
@@ -27,6 +27,7 @@ void State::BindRasterizer(VideoCore::RasterizerInterface* rasterizer_) {
 
 void State::ProcessExec(const bool is_linear_) {
     write_offset = 0;
+    flushed_offset = 0;
     copy_size = regs.line_length_in * regs.line_count;
     inner_buffer.resize_destructive(copy_size);
     is_linear = is_linear_;
@@ -39,10 +40,29 @@ void State::ProcessData(const u32 data, const bool is_last_call) {
     if (!is_last_call) {
         return;
     }
+    if (native_partial && is_linear && regs.line_count == 1) {
+        const u32 count = write_offset - flushed_offset;
+        if (count) {
+            rasterizer->AccelerateInlineToMemory(regs.dest.Address() + flushed_offset, count,
+                std::span<const u8>{inner_buffer.data() + flushed_offset, count});
+            flushed_offset = write_offset;
+        }
+        return;
+    }
     ProcessData(inner_buffer);
 }
 
 void State::ProcessData(const u32* data, size_t num_data) {
+    if (native_partial && is_linear && regs.line_count == 1) {
+        const auto count = std::min<size_t>(num_data * sizeof(u32), copy_size - write_offset);
+        if (count) {
+            rasterizer->AccelerateInlineToMemory(regs.dest.Address() + write_offset, count,
+                std::span<const u8>{reinterpret_cast<const u8*>(data), count});
+            write_offset += static_cast<u32>(count);
+            flushed_offset = write_offset;
+        }
+        return;
+    }
     std::span<const u8> read_buffer(reinterpret_cast<const u8*>(data), num_data * sizeof(u32));
     ProcessData(read_buffer);
 }