Switch 2 GPU: syncpt server, identity GPU mappings, Ampere classes, submit fences

- gsv 204: real syncpoint shared page (values mirrored from host1x, armed waits
  acknowledged by a 500us poller); first handle is the writable request event.
- syncpt 22/201/202: per-slot events signalled through host1x guest actions.
- nx2:gpu sub 101 memory is identity-mapped (GPU VA == CPU VA) into every
  nvhost-as-gpu GMMU via Nx2GpuMemoryRegistry; SMMU physical range widened to
  34 bits for the 10/12 GiB layouts.
- Puller runs Ampere 3D/compute/copy classes on the Maxwell engines; class 0 unbinds.
- Turing+ macros are skipped (Eden only has the Fermi macro ISA).
- Submits with increment_value get Eden-side syncpoint increments, since NVN2
  signals completion with semaphore releases only.

1 files changed, 7 insertions, 0 deletions

diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index e7da9d9138..1a43133296 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -12,6 +12,7 @@
 #include "common/settings.h"
 #include "core/core.h"
 #include "core/core_timing.h"
+#include "video_core/nx2.h"
 #include "video_core/dirty_flags.h"
 #include "video_core/engines/maxwell_3d.h"
 #include "video_core/engines/maxwell_3d.h"
@@ -380,6 +381,12 @@ void Maxwell3D::CallMacroMethod(Core::System& system, u32 method, const std::vec
     const u32 entry =
         ((method - MacroRegistersStart) >> 1) % static_cast<u32>(macro_positions.size());
 
+    // Switch 2 uploads Turing+ (MME64) macros, which Eden's Fermi-style macro engine can't run.
+    if (g_nx2_ampere) {
+        LOG_DEBUG(HW_GPU, "Switch 2 macro {} with {} parameters skipped", entry, parameters.size());
+        return;
+    }
+
     // Execute the current macro.
     macro_engine.Execute(system, *this, macro_positions[entry], parameters);
     draw_manager.DrawDeferred(*this);