Switch 2: per-channel MME data RAM; one QMD table for all channels

Macro code stays shared by the channels of a process, but each channel
now has its own MME data RAM. Title 1's channels keep their own QMD ring
base in data word 0x27; with one shared RAM every channel used the last
channel's ring, QMDs collided, releases came early or never and the GPU
waited on semaphores (4 s timeouts per frame).

The QMD scheduler state is one table for all channels: a QMD's
dependency counter is state of the QMD, scheduled and decremented from
different channels.

Diagnostics: EDEN_NX2_QMD_TRACE (scheduler loads, counts, launches) and
EDEN_NX2_MME_DUMP (compute macro code, calls, data word 0x27 changes).

1 files changed, 10 insertions, 5 deletions

diff --git a/src/video_core/macro_turing.h b/src/video_core/macro_turing.h
index a0a40000c2..063e22c297 100644
--- a/src/video_core/macro_turing.h
+++ b/src/video_core/macro_turing.h
@@ -167,11 +167,11 @@ public:
                     }
                     break;
                 case 30:
-                    if (x >= dram.size()) { fail("data RAM read out of bounds"); break; }
-                    value = dram[x]; break;
+                    if (x >= active_dram->size()) { fail("data RAM read out of bounds"); break; }
+                    value = (*active_dram)[x]; break;
                 case 31:
-                    if (x >= dram.size()) { fail("data RAM write out of bounds"); break; }
-                    dram[x] = y; break;
+                    if (x >= active_dram->size()) { fail("data RAM write out of bounds"); break; }
+                    (*active_dram)[x] = y; break;
                 }
                 alu[lane] = value;
                 if (dst[lane] < 24) { regs[dst[lane]] = value; initialized |= 1U << dst[lane]; }
@@ -209,7 +209,12 @@ public:
         return {false, pc, consumed, error};
     }
 
-    std::array<Word, 0xc00> dram{};
+    using DataRam = std::array<Word, 0xc00>;
+    DataRam dram{};
+    // The data RAM DREAD/DWRITE use: a channel's own copy when the caller sets one. Macro code is
+    // shared by the channels of a process, but each channel keeps its own data RAM (title 1's
+    // channels store their own QMD ring base in word 0x27).
+    DataRam* active_dram{&dram};
 };
 
 } // namespace Tegra