diff options
| author | Ribbit <ribbit@eden-emu.dev> | 2025-10-16 03:33:24 +0200 |
|---|---|---|
| committer | crueter <crueter@eden-emu.dev> | 2025-10-16 03:33:24 +0200 |
| commit | 30482692c77dfc1e8f95c393e9e9734178c50ae4 (patch) | |
| tree | 731edf3e87787a7476c22330f07b8369c3a850e4 /src/video_core/renderer_vulkan/present/layer.cpp | |
| parent | 31463142e1537c931370b8e1b6b470ce810074b7 (diff) | |
Revert "[vk] Fix Vulkan Upload & Present Barriers for Spec Compliance (#2681)" (#2748)
Vulkan layout and barrier edits made the GPU use a different shader path that compiled a TLDS instruction with an unaligned register (R157).
The old path never generated that case, so the translator’s missing unaligned-register handling only surfaced after this change.
Co-authored-by: Ribbit <ribbit@placeholder.com>
Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/2748
Reviewed-by: MaranBr <maranbr@eden-emu.dev>
Co-authored-by: Ribbit <ribbit@eden-emu.dev>
Co-committed-by: Ribbit <ribbit@eden-emu.dev>
Diffstat (limited to 'src/video_core/renderer_vulkan/present/layer.cpp')
| -rw-r--r-- | src/video_core/renderer_vulkan/present/layer.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/video_core/renderer_vulkan/present/layer.cpp b/src/video_core/renderer_vulkan/present/layer.cpp index fee19a69c2..5676dfe62a 100644 --- a/src/video_core/renderer_vulkan/present/layer.cpp +++ b/src/video_core/renderer_vulkan/present/layer.cpp @@ -332,7 +332,7 @@ void Layer::UpdateRawImage(const Tegra::FramebufferConfig& framebuffer, size_t i write_barrier.dstAccessMask = VK_ACCESS_SHADER_READ_BIT; write_barrier.oldLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL; - cmdbuf.PipelineBarrier(VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT, VK_PIPELINE_STAGE_TRANSFER_BIT, 0, + cmdbuf.PipelineBarrier(VK_PIPELINE_STAGE_HOST_BIT, VK_PIPELINE_STAGE_TRANSFER_BIT, 0, read_barrier); cmdbuf.CopyBufferToImage(*buffer, image, VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL, copy); cmdbuf.PipelineBarrier(VK_PIPELINE_STAGE_TRANSFER_BIT, |