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| author | Fernando Sahmkow <fsahmkow27@gmail.com> | 2019-07-18 08:17:19 -0400 |
|---|---|---|
| committer | Fernando Sahmkow <fsahmkow27@gmail.com> | 2019-07-18 08:17:19 -0400 |
| commit | a13b47f080bdfdb08ccf00c806e21be2a80654fc (patch) | |
| tree | eadd594ef4e32149cbd2aaf10e523daf89483c87 /src/video_core/shader/decode/arithmetic.cpp | |
| parent | 7d38c526fe4098c8dd5f0d725a97aba06c07da03 (diff) | |
Shader_Ir: Downgrade precision and rounding asserts to debug asserts.
This commit reduces the sevirity of asserts for FP precision and
rounding as this are well known and have little to no consequences in
gpu's accuracy.
Diffstat (limited to 'src/video_core/shader/decode/arithmetic.cpp')
| -rw-r--r-- | src/video_core/shader/decode/arithmetic.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/video_core/shader/decode/arithmetic.cpp b/src/video_core/shader/decode/arithmetic.cpp index 87d8fecaa3..05a5f19d28 100644 --- a/src/video_core/shader/decode/arithmetic.cpp +++ b/src/video_core/shader/decode/arithmetic.cpp @@ -42,10 +42,10 @@ u32 ShaderIR::DecodeArithmetic(NodeBlock& bb, u32 pc) { case OpCode::Id::FMUL_R: case OpCode::Id::FMUL_IMM: { // FMUL does not have 'abs' bits and only the second operand has a 'neg' bit. - UNIMPLEMENTED_IF_MSG(instr.fmul.tab5cb8_2 != 0, "FMUL tab5cb8_2({}) is not implemented", - instr.fmul.tab5cb8_2.Value()); - UNIMPLEMENTED_IF_MSG( - instr.fmul.tab5c68_0 != 1, "FMUL tab5cb8_0({}) is not implemented", + DEBUG_ASSERT_MSG(instr.fmul.tab5cb8_2 == 0, "FMUL tab5cb8_2({}) is not implemented", + instr.fmul.tab5cb8_2.Value()); + DEBUG_ASSERT_MSG( + instr.fmul.tab5c68_0 == 1, "FMUL tab5cb8_0({}) is not implemented", instr.fmul.tab5c68_0.Value()); // SMO typical sends 1 here which seems to be the default op_b = GetOperandAbsNegFloat(op_b, false, instr.fmul.negate_b); |