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| author | Takoroka <137927095+Takoroka@users.noreply.github.com> | 2026-10-30 14:44:01 -0400 |
|---|---|---|
| committer | Takoroka <137927095+Takoroka@users.noreply.github.com> | 2026-11-01 11:09:53 -0500 |
| commit | cefcf3a9b1c78250a53aa241fc3cd5d4e5b30f26 (patch) | |
| tree | 64e9b106796be51a8d2e4c5daf2eeb1f449e2d5c /src/video_core/shader_cache.cpp | |
| parent | 01389ee5266fe5e775ef205ca90122d68d4c46c5 (diff) | |
nx2: keep the uniform clamp before a jump table when instructions sit between
A jump table index clamped with UISETP.LT.U32 UP0, UPT, URa, n and
USEL URa, URa, n, UP0 is lowered to IMNMX.U32 so Maxwell's indirect
branch tracker can size the table, but only when the UISETP came right
before the USEL. Nintendo Switch Sports Resort's pixel shaders put
ordinary ALU instructions between them, so the USEL became a SEL, the
BRXU could not be tracked and 6 pipelines failed ("Failed to track
indirect branch"). Look back up to 8 instructions, stopping at any that
could write uniform state or branch, or that a branch seen so far lands
on.
Diffstat (limited to 'src/video_core/shader_cache.cpp')
0 files changed, 0 insertions, 0 deletions
