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authorTakoroka <137927095+Takoroka@users.noreply.github.com>2026-10-27 19:30:20 -0400
committerTakoroka <137927095+Takoroka@users.noreply.github.com>2026-10-27 19:30:20 -0400
commitf32b430326af86bd956f3d49d1bf7b6a1b9c5e31 (patch)
tree4dc321c41055bd68f1e1bb6707330df1ee9599fa /src/video_core/texture_cache/accelerated_swizzle.cpp
parenta750204a15561e8e22d40c50df8e0827eb45fd8f (diff)
Switch 2: native memory/images, GPU-accessible attribute, TSG subcontexts, syncpoint shim
- gsv 111/112/114/423/429/430/314/315/435 track native memory and images with real ids (meanings from changes.patch); 1510/435 use its block-linear layout. - svc 0x80 sets a real GpuAccessible (0x20) memory attribute (from changes.patch). - Characteristics report TSG subcontexts (flag 22, 64 per TSG at 0xb4); NvRm otherwise allows one subcontext and a second NVN queue fails its setup. - Syncpoint shim: flag 26, address-space ioctl 0xB, and GPU reads of the shim page return guest syncpoint values (scheme from changes.patch). - EDEN_NX2_IPC_TRACE also logs TIPC commands; gdbrsp.py watch/mem improvements.
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