Revert "Import experimental NS2 support and accumulated GPU fixes"

This reverts commit 535b676970. The Switch 2 support comes from the nx2
work instead, merged next.

1 files changed, 4 insertions, 4 deletions

diff --git a/src/video_core/texture_cache/util.cpp b/src/video_core/texture_cache/util.cpp
index 5bcea68977..e55d0752ec 100644
--- a/src/video_core/texture_cache/util.cpp
+++ b/src/video_core/texture_cache/util.cpp
@@ -439,7 +439,7 @@ template <u32 GOB_EXTENT>
         }
         layers = 1;
     } else {
-        layers = (std::max)(info.resources.layers, resources.layers + base->layer);
+        layers = (std::max)(resources.layers, info.resources.layers + base->layer);
     }
     return OverlapResult{
         .gpu_addr = overlap.gpu_addr,
@@ -566,7 +566,7 @@ void SwizzleBlockLinearImage(Tegra::MemoryManager& gpu_memory, GPUVAddr gpu_addr
                 dst(gpu_memory, gpu_addr + guest_offset, subresource_size, &tmp_buffer);
 
             SwizzleTexture(dst, src, bytes_per_block, num_tiles.width, num_tiles.height,
-                           num_tiles.depth, block.height, block.depth, 1, gpu_memory.UsesNativeTiling());
+                           num_tiles.depth, block.height, block.depth);
         }
 
         host_offset += host_bytes_per_layer;
@@ -838,7 +838,7 @@ bool IsValidEntry(const Tegra::MemoryManager& gpu_memory, const TICEntry& config
     if (gpu_memory.GpuToCpuAddress(address).has_value()) {
         return true;
     }
-    const ImageInfo info{TextureViewHeader(config, gpu_memory.UsesNativeTiling())};
+    const ImageInfo info{config};
     const size_t guest_size_bytes = CalculateGuestSizeInBytes(info);
     return gpu_memory.GpuToCpuAddress(address, guest_size_bytes).has_value();
 }
@@ -913,7 +913,7 @@ boost::container::small_vector<BufferImageCopy, 16> UnswizzleImage(Tegra::Memory
             const std::span<u8> dst = output.subspan(host_offset);
             const std::span<const u8> src = input.subspan(guest_offset + guest_layer_offset);
             UnswizzleTexture(dst, src, 1U << bpp_log2, num_tiles.width, num_tiles.height,
-                             num_tiles.depth, block.height, block.depth, stride_alignment, gpu_memory.UsesNativeTiling());
+                             num_tiles.depth, block.height, block.depth, stride_alignment);
             guest_layer_offset += layer_stride;
             host_offset += host_bytes_per_layer;
         }