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authorTakoroka <137927095+Takoroka@users.noreply.github.com>2026-10-27 14:57:51 -0400
committerTakoroka <137927095+Takoroka@users.noreply.github.com>2026-10-27 14:57:51 -0400
commit58e1e35e1026d1a3eac87a82a22ac28bdbea8dc3 (patch)
tree024699c3a7cb2360b1f2b626d52226bad46d5c6a /NX2_NOTES.md
parentb04c1af7890335abc82526ba539db0a24515afb4 (diff)
nvdrv: Switch 2 GPU address-space layout; gpu 33/203
- AllocAsEx from Switch 2 NvRm passes flags 5, no big page size, range [0x8000000, 0xC000000000) and split 0 (small pages only). Treat split 0 as small pages up to the end, keep a 4 GiB big-page region after it, and give that allocator an absolute limit (Eden's length-as-limit breaks once the split is past the region length). - gpu TIPC 33 returns a count, 203 a kind plus a VA range used by nn::gpu::sdk::CreateGpuAddressSpace. - gdbrsp.py: unbreak, step, breaklr, unbreakpc, fp (frame walk), trace.
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