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authorReinUsesLisp <reinuseslisp@airmail.cc>2021-05-25 02:22:21 -0300
committerameerj <52414509+ameerj@users.noreply.github.com>2021-07-22 21:51:33 -0400
commit143db4b112ce2fad78b86ab95f11cb301887b226 (patch)
tree813638ab0c537089f3493f824707417dd429a48f /src/shader_recompiler/backend/glasm/reg_alloc.cpp
parenta5ce5f4a6547052d99112a26754870cc4d7880a7 (diff)
glasm: Catch more register leaks
Add support for null registers. These are used when an instruction has no usages. This comes handy when an instruction is only used for its CC value, with the caveat of having to invalidate all pseudo-instructions before defining the instruction itself in the register allocator. This commits changes this. Workaround a bug on Nvidia's condition codes conditional execution using branches.
Diffstat (limited to 'src/shader_recompiler/backend/glasm/reg_alloc.cpp')
-rw-r--r--src/shader_recompiler/backend/glasm/reg_alloc.cpp28
1 files changed, 24 insertions, 4 deletions
diff --git a/src/shader_recompiler/backend/glasm/reg_alloc.cpp b/src/shader_recompiler/backend/glasm/reg_alloc.cpp
index 707b22247a..c55a833c6d 100644
--- a/src/shader_recompiler/backend/glasm/reg_alloc.cpp
+++ b/src/shader_recompiler/backend/glasm/reg_alloc.cpp
@@ -22,11 +22,19 @@ Register RegAlloc::LongDefine(IR::Inst& inst) {
}
Value RegAlloc::Peek(const IR::Value& value) {
- return value.IsImmediate() ? MakeImm(value) : PeekInst(*value.InstRecursive());
+ if (value.IsImmediate()) {
+ return MakeImm(value);
+ } else {
+ return PeekInst(*value.Inst());
+ }
}
Value RegAlloc::Consume(const IR::Value& value) {
- return value.IsImmediate() ? MakeImm(value) : ConsumeInst(*value.InstRecursive());
+ if (value.IsImmediate()) {
+ return MakeImm(value);
+ } else {
+ return ConsumeInst(*value.Inst());
+ }
}
void RegAlloc::Unref(IR::Inst& inst) {
@@ -88,7 +96,14 @@ Value RegAlloc::MakeImm(const IR::Value& value) {
}
Register RegAlloc::Define(IR::Inst& inst, bool is_long) {
- inst.SetDefinition<Id>(Alloc(is_long));
+ if (inst.HasUses()) {
+ inst.SetDefinition<Id>(Alloc(is_long));
+ } else {
+ Id id{};
+ id.is_long.Assign(is_long ? 1 : 0);
+ id.is_null.Assign(1);
+ inst.SetDefinition<Id>(id);
+ }
return Register{PeekInst(inst)};
}
@@ -115,10 +130,12 @@ Id RegAlloc::Alloc(bool is_long) {
num_regs = std::max(num_regs, reg + 1);
use[reg] = true;
Id ret{};
- ret.index.Assign(static_cast<u32>(reg));
+ ret.is_valid.Assign(1);
ret.is_long.Assign(is_long ? 1 : 0);
ret.is_spill.Assign(0);
ret.is_condition_code.Assign(0);
+ ret.is_null.Assign(0);
+ ret.index.Assign(static_cast<u32>(reg));
return ret;
}
}
@@ -126,6 +143,9 @@ Id RegAlloc::Alloc(bool is_long) {
}
void RegAlloc::Free(Id id) {
+ if (id.is_valid == 0) {
+ throw LogicError("Freeing invalid register");
+ }
if (id.is_spill != 0) {
throw NotImplementedException("Free spill");
}