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authorTakoroka <137927095+Takoroka@users.noreply.github.com>2026-10-27 17:04:06 -0400
committerTakoroka <137927095+Takoroka@users.noreply.github.com>2026-10-27 17:04:06 -0400
commitdce3adbc4cae486e2f3c080b995669d6db5ef58f (patch)
tree638ec3ffef50441c7229160ee20b0fd9423ee271 /src/video_core/nx2.h
parent2835fec7fc66e1a1659710de8eddf2dfe67e20f9 (diff)
Switch 2: window image sizes, queue semaphores, built-in fonts, memory budget
- gsv 1510 CalculateRequirements: block-linear size/alignment for window images. - nvhost-gpu: Switch 2 channel event 7 is a real (unsignalled) event. - Puller mirrors NVN2 queue semaphore releases into the page the CPU and GPU wait on (the first two-page nx2:gpu region); EDEN_NX2_METHOD_TRACE logs methods. - pl:u 2000/2010 GetBuiltInFontSharedMemory/GetBuiltInFontData serve plain TTF copies of the shared fonts. - Switch 2 processes count the alias region in their max memory, so the game's nninitStartup heap (total - 6.3 GiB) has room for its sound heap. - gdbrsp.py: interrupt, threads, selthread, hits, continue_async, sleep.
Diffstat (limited to 'src/video_core/nx2.h')
-rw-r--r--src/video_core/nx2.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/video_core/nx2.h b/src/video_core/nx2.h
index b8258ca243..9fdf0a7c68 100644
--- a/src/video_core/nx2.h
+++ b/src/video_core/nx2.h
@@ -5,10 +5,18 @@
#include <atomic>
+#include "common/common_types.h"
+
namespace Tegra {
// Set once a Switch 2 (Ampere, NVN2) driver is talking to the GPU. Its command streams use
// Ampere classes and the Turing+ macro ISA, which Eden's Maxwell engines don't implement.
inline std::atomic<bool> g_nx2_ampere{false};
+// NVN2 queues release their progress values into one GPU page and wait (GPU acquires and CPU
+// polls) on the same offsets in the page below it. Something on the console copies one into
+// the other; until that is known, the puller mirrors releases that land in the source page.
+inline std::atomic<u64> g_nx2_semaphore_source_page{0}; // GPU VA of the released-to page
+inline std::atomic<u64> g_nx2_semaphore_mirror_page{0}; // GPU VA of the waited-on page
+
} // namespace Tegra