diff options
| author | kraibse <33869366+kraibse@users.noreply.github.com> | 2026-11-01 21:44:43 +0100 |
|---|---|---|
| committer | kraibse <33869366+kraibse@users.noreply.github.com> | 2026-11-01 21:45:14 +0100 |
| commit | 70d291d3aaabac45a41e458f5e26b9590db57ea5 (patch) | |
| tree | 91bc075c324eb036a4897d0a732f65cece1478b6 /src | |
| parent | 12d9386e7ef1f27984054d80c493a06c5fa2124c (diff) | |
Revert "nx2/ampere: implement ISBERD (0x923) and accept ISBEWR (0x927)"
This reverts commit d9e4ac8360b3b63b7ddba05757c87e867f9163fa.
Diffstat (limited to 'src')
| -rw-r--r-- | src/shader_recompiler/frontend/ampere/lower_to_maxwell.h | 30 |
1 files changed, 0 insertions, 30 deletions
diff --git a/src/shader_recompiler/frontend/ampere/lower_to_maxwell.h b/src/shader_recompiler/frontend/ampere/lower_to_maxwell.h index b0888503e5..031f7fac75 100644 --- a/src/shader_recompiler/frontend/ampere/lower_to_maxwell.h +++ b/src/shader_recompiler/frontend/ampere/lower_to_maxwell.h @@ -2251,36 +2251,6 @@ inline LoweredProgram LowerToMaxwell(std::span<const Instruction> code) { main_exited = true; break; } - case 0x923: { // ISBERD: leitura do buffer de entrada de estagio (mapa/patch/primitiva/atributo). - // Layout Ampere (Mesa NAK sm70_encode.rs, OpIsberd): dst 16-23, offset 24-31, - // imm 40-55, mem_type 74-75, access 76-77, skew 78, output 79. - const u32 offset_reg = insn.Bits(24, 8); - const u32 imm_offset = insn.Bits(40, 16); - const u32 mem_type = insn.Bits(74, 2); - const u32 access = insn.Bits(76, 2); - const u32 skew = insn.Bits(78, 1); - const u32 output = insn.Bits(79, 1); - if (imm_offset > 0xff || mem_type > 2 || (offset_reg != 255 && offset_reg >= 246)) - return fail(index, "native stage buffer entry read mode"); - // Maxwell ISBERD (maxwell.inc: "1110 1111 1101 0---"): dst 0-7, src 8-15, - // imm 24-31, skew 31, o 32, mode 33-34, sz 36-39, shift 47-48 (Default = 0). - // O frontend Maxwell ja implementa a semantica completa (patches, primitivas, - // atributos indexados e leitura global com skew por lane). - emit(0xefd0000000000000ULL | predicate | dest | (u64{offset_reg} << 8) | - (u64{imm_offset} << 24) | (u64{skew} << 31) | (u64{output} << 32) | - (u64{access} << 33) | (u64{mem_type} << 36)); - break; - } - case 0x927: { // ISBEWR: escrita no buffer de entrada de estagio (saida de patch/atributo). - // O frontend Maxwell nao tem ISBEWR, entao a escrita e descartada: preferivel a - // rejeitar o programa inteiro (o objeto/efeito desaparecia da cena). - const u32 offset_reg = insn.Bits(24, 8); - const u32 data_reg = insn.Bits(32, 8); - // 255 = RZ: vale como "sem deslocamento" e como dado zero. - if ((offset_reg != 255 && offset_reg >= 246) || (data_reg != 255 && data_reg >= 246)) - return fail(index, "native stage buffer entry write registers"); - break; - } default: return fail(index, "unsupported native opcode"); } |
