diff options
| author | Takoroka <137927095+Takoroka@users.noreply.github.com> | 2026-11-02 02:14:34 -0500 |
|---|---|---|
| committer | Takoroka <137927095+Takoroka@users.noreply.github.com> | 2026-11-02 02:14:34 -0500 |
| commit | 9210b8d69d172b5456e90cbd56b8f2bacbd7386b (patch) | |
| tree | b480b37fefa466acb07b95b4b10cb429c64be68c /src | |
| parent | 2a80edb6d3d7b7f2fd2bba11cc30d399e02ba7e9 (diff) | |
| parent | 6be5c163338d2025bc36eeb376efc9311957be1a (diff) | |
Merge branch 'fix/nx2-hsetp2-register' into nx2-experimental
Diffstat (limited to 'src')
| -rw-r--r-- | src/shader_recompiler/frontend/ampere/lower_to_maxwell.h | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/src/shader_recompiler/frontend/ampere/lower_to_maxwell.h b/src/shader_recompiler/frontend/ampere/lower_to_maxwell.h index b7f74b8901..4ce374ce61 100644 --- a/src/shader_recompiler/frontend/ampere/lower_to_maxwell.h +++ b/src/shader_recompiler/frontend/ampere/lower_to_maxwell.h @@ -2153,11 +2153,20 @@ inline LoweredProgram LowerToMaxwellWith(std::span<const Instruction> code, u32 (u64{insn.Bits(76, 4)} << 48) | (u64{1} << 52) | (u64{insn.Bits(80, 1)} << 55)); break; } - case 0x434: { // HSETP2 with an immediate half pair: A swizzle 74-75 (neg 72, abs 73), + case 0x234: case 0x434: { // HSETP2 with a register (B swizzle 60-61, abs 62, neg 63) or an + // immediate half pair: A swizzle 74-75 (neg 72, abs 73), // combine 69-70, H_AND 71, compare 76-79, FTZ 80, P/Q 81-86, input 87-90. - mov_imm(250, insn.words[1]); + u64 source = u64{250} << 20; + if (opcode == 0x234) { + if ((insn.words[1] & 0x0fffff00U) || insn.Bits(64, 5)) + return fail(index, "native half comparison mode"); + source = (u64{insn.Bits(32, 8)} << 20) | (u64{insn.Bits(60, 2)} << 28) | + (u64{insn.Bits(62, 1)} << 30) | (u64{insn.Bits(63, 1)} << 31); + } else { + mov_imm(250, insn.words[1]); + } emit(0x5d20000000000000ULL | predicate | insn.Bits(84, 3) | (u64{insn.Bits(81, 3)} << 3) | - (u64{insn.Bits(80, 1)} << 6) | (u64{insn.Bits(24, 8)} << 8) | (u64{250} << 20) | + (u64{insn.Bits(80, 1)} << 6) | (u64{insn.Bits(24, 8)} << 8) | source | (u64{insn.Bits(76, 4)} << 35) | (u64{insn.Bits(87, 3)} << 39) | (u64{insn.Bits(90, 1)} << 42) | (u64{insn.Bits(72, 1)} << 43) | (u64{insn.Bits(73, 1)} << 44) | (u64{insn.Bits(69, 2)} << 45) | |