diff options
| author | Takoroka <137927095+Takoroka@users.noreply.github.com> | 2026-10-29 20:44:40 -0400 |
|---|---|---|
| committer | Takoroka <137927095+Takoroka@users.noreply.github.com> | 2026-10-29 20:49:49 -0400 |
| commit | b09f5339c1e621340f2d3a12ff40b256f5419253 (patch) | |
| tree | 499124dbb0de9c51a3257a028d44e53752438f4f /src | |
| parent | 2203754e5d054ad2e2d68dd15a3aa3bf0db2479b (diff) | |
shader: compare the native FMUL/FADD mode bits as integers
MSVC warns (C4805) about comparing a u32 bit field with a bool.
Diffstat (limited to 'src')
| -rw-r--r-- | src/shader_recompiler/frontend/ampere/lower_to_maxwell.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/shader_recompiler/frontend/ampere/lower_to_maxwell.h b/src/shader_recompiler/frontend/ampere/lower_to_maxwell.h index 2663f3a830..0bed72eaec 100644 --- a/src/shader_recompiler/frontend/ampere/lower_to_maxwell.h +++ b/src/shader_recompiler/frontend/ampere/lower_to_maxwell.h @@ -1721,7 +1721,7 @@ inline LoweredProgram LowerToMaxwell(std::span<const Instruction> code) { case 0x220: case 0x820: case 0xa20: case 0xc20: { // FMUL const u32 scale = insn.Bits(84, 3); if (insn.Bits(76, 1) || scale == 0 || insn.Bits(81, 3) || - insn.Bits(87, 4) || insn.Bits(91, 1) != (opcode == 0xc20) || + insn.Bits(87, 4) || insn.Bits(91, 1) != static_cast<u32>(opcode == 0xc20) || (scale != 4 && (!insn.Bits(80, 1) || insn.Bits(78, 2)))) return fail(index, "native FMUL scale/mode"); const u32 a = operand(0), b = operand(1); @@ -1730,7 +1730,8 @@ inline LoweredProgram LowerToMaxwell(std::span<const Instruction> code) { break; } case 0x221: case 0x421: case 0x621: case 0x821: case 0xa21: case 0xe21: { // FADD - if (insn.Bits(81, 10) || insn.Bits(91, 1) != (opcode == 0xe21)) return fail(index, "native FADD mode"); + if (insn.Bits(81, 10) || insn.Bits(91, 1) != static_cast<u32>(opcode == 0xe21)) + return fail(index, "native FADD mode"); const u32 a = operand(0), b = operand(insn.Bits(9, 3) == 2 || insn.Bits(9, 3) == 3 || insn.Bits(9, 3) == 7 ? 2 : 1); emit(base(0x5c58000000000000ULL) | (u64{a} << 8) | (u64{b} << 20) | (u64{insn.Bits(78, 2)} << 39) | (u64{insn.Bits(80, 1)} << 44) | (u64{insn.Bits(77, 1)} << 50)); |