diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/pte_kind.h | 70 |
1 files changed, 30 insertions, 40 deletions
diff --git a/src/video_core/pte_kind.h b/src/video_core/pte_kind.h index 591d7214b2..d1495d94b0 100644 --- a/src/video_core/pte_kind.h +++ b/src/video_core/pte_kind.h @@ -1,3 +1,6 @@ +// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project +// SPDX-License-Identifier: GPL-3.0-or-later + // SPDX-FileCopyrightText: Copyright 2022 yuzu Emulator Project // SPDX-License-Identifier: GPL-2.0-or-later @@ -9,28 +12,22 @@ namespace Tegra { // https://github.com/NVIDIA/open-gpu-doc/blob/master/manuals/volta/gv100/dev_mmu.ref.txt enum class PTEKind : u8 { - INVALID = 0xff, - PITCH = 0x00, - Z16 = 0x01, - Z16_2C = 0x02, - Z16_MS2_2C = 0x03, - Z16_MS4_2C = 0x04, - Z16_MS8_2C = 0x05, - Z16_MS16_2C = 0x06, - Z16_2Z = 0x07, - Z16_MS2_2Z = 0x08, - Z16_MS4_2Z = 0x09, - Z16_MS8_2Z = 0x0a, - Z16_MS16_2Z = 0x0b, - Z16_2CZ = 0x36, - Z16_MS2_2CZ = 0x37, - Z16_MS4_2CZ = 0x38, - Z16_MS8_2CZ = 0x39, - Z16_MS16_2CZ = 0x5f, - Z16_4CZ = 0x0c, - Z16_MS2_4CZ = 0x0d, - Z16_MS4_4CZ = 0x0e, - Z16_MS8_4CZ = 0x0f, + PITCH = 0x0, + Z16 = 0x1, + Z16_2C = 0x2, + Z16_MS2_2C = 0x3, + Z16_MS4_2C = 0x4, + Z16_MS8_2C = 0x5, + Z16_MS16_2C = 0x6, + Z16_2Z = 0x7, + Z16_MS2_2Z = 0x8, + Z16_MS4_2Z = 0x9, + Z16_MS8_2Z = 0xa, + Z16_MS16_2Z = 0xb, + Z16_4CZ = 0xc, + Z16_MS2_4CZ = 0xd, + Z16_MS4_4CZ = 0xe, + Z16_MS8_4CZ = 0xf, Z16_MS16_4CZ = 0x10, S8Z24 = 0x11, S8Z24_1Z = 0x12, @@ -43,7 +40,7 @@ enum class PTEKind : u8 { S8Z24_MS4_2CZ = 0x19, S8Z24_MS8_2CZ = 0x1a, S8Z24_MS16_2CZ = 0x1b, - S8Z24_2CS = 0x1c, + S8Z24_2CS = 0x1C, S8Z24_MS2_2CS = 0x1d, S8Z24_MS4_2CS = 0x1e, S8Z24_MS8_2CS = 0x1f, @@ -57,6 +54,8 @@ enum class PTEKind : u8 { V8Z24_MS4_VC4 = 0x27, V8Z24_MS8_VC8 = 0x28, V8Z24_MS8_VC24 = 0x29, + S8 = 0x2a, + S8_2S = 0x2b, V8Z24_MS4_VC12_1ZV = 0x2e, V8Z24_MS4_VC4_1ZV = 0x2f, V8Z24_MS8_VC8_1ZV = 0x30, @@ -99,15 +98,9 @@ enum class PTEKind : u8 { Z24S8_MS8_4CSZV = 0x59, Z24S8_MS16_4CSZV = 0x5a, Z24V8_MS4_VC12 = 0x5b, - Z24V8_MS4_VC4 = 0x5c, + Z24V8_MS4_VC4 = 0x5C, Z24V8_MS8_VC8 = 0x5d, Z24V8_MS8_VC24 = 0x5e, - YUV_B8C1_2Y = 0x60, - YUV_B8C2_2Y = 0x61, - YUV_B10C1_2Y = 0x62, - YUV_B10C2_2Y = 0x6b, - YUV_B12C1_2Y = 0x6c, - YUV_B12C2_2Y = 0x6d, Z24V8_MS4_VC12_1ZV = 0x63, Z24V8_MS4_VC4_1ZV = 0x64, Z24V8_MS8_VC8_1ZV = 0x65, @@ -129,7 +122,7 @@ enum class PTEKind : u8 { Z24V8_MS8_VC8_4CSZV = 0x79, Z24V8_MS8_VC24_4CSZV = 0x7a, ZF32 = 0x7b, - ZF32_1Z = 0x7c, + ZF32_1Z = 0x7C, ZF32_MS2_1Z = 0x7d, ZF32_MS4_1Z = 0x7e, ZF32_MS8_1Z = 0x7f, @@ -198,6 +191,9 @@ enum class PTEKind : u8 { ZF32_X24S8_MS4_1CS = 0xc6, ZF32_X24S8_MS8_1CS = 0xc7, ZF32_X24S8_MS16_1CS = 0xc8, + SMASKED_MESSAGE = 0xca, + SMHOST_MESSAGE = 0xcb, + C64_MS2_2CRA = 0xcd, ZF32_X24S8_2CSZV = 0xce, ZF32_X24S8_MS2_2CSZV = 0xcf, ZF32_X24S8_MS4_2CSZV = 0xd0, @@ -208,9 +204,6 @@ enum class PTEKind : u8 { ZF32_X24S8_MS4_2CS = 0xd5, ZF32_X24S8_MS8_2CS = 0xd6, ZF32_X24S8_MS16_2CS = 0xd7, - S8 = 0x2a, - S8_2S = 0x2b, - GENERIC_16BX2 = 0xfe, C32_2C = 0xd8, C32_2CBR = 0xd9, C32_2CBA = 0xda, @@ -218,13 +211,12 @@ enum class PTEKind : u8 { C32_2BRA = 0xdc, C32_MS2_2C = 0xdd, C32_MS2_2CBR = 0xde, - C32_MS2_4CBRA = 0xcc, + C32_MS2_2CRA = 0xcc, C32_MS4_2C = 0xdf, C32_MS4_2CBR = 0xe0, C32_MS4_2CBA = 0xe1, C32_MS4_2CRA = 0xe2, C32_MS4_2BRA = 0xe3, - C32_MS4_4CBRA = 0x2c, C32_MS8_MS16_2C = 0xe4, C32_MS8_MS16_2CRA = 0xe5, C64_2C = 0xe6, @@ -234,13 +226,11 @@ enum class PTEKind : u8 { C64_2BRA = 0xea, C64_MS2_2C = 0xeb, C64_MS2_2CBR = 0xec, - C64_MS2_4CBRA = 0xcd, C64_MS4_2C = 0xed, C64_MS4_2CBR = 0xee, C64_MS4_2CBA = 0xef, C64_MS4_2CRA = 0xf0, C64_MS4_2BRA = 0xf1, - C64_MS4_4CBRA = 0x2d, C64_MS8_MS16_2C = 0xf2, C64_MS8_MS16_2CRA = 0xf3, C128_2C = 0xf4, @@ -253,8 +243,8 @@ enum class PTEKind : u8 { C128_MS8_MS16_2CR = 0xfb, X8C24 = 0xfc, PITCH_NO_SWIZZLE = 0xfd, - SMSKED_MESSAGE = 0xca, - SMHOST_MESSAGE = 0xcb, + GENERIC_16BX2 = 0xfe, + INVALID = 0xff, }; constexpr bool IsPitchKind(PTEKind kind) { |