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* Merge pull request #304 from rdenno/fix/hw-shader-loweringJonas25 hours1-10/+43
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| * Merge branch 'nx2-experimental' into fix/hw-shader-loweringrdenno34 hours2-95/+381
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| * | shader: lower TXD with any channel maskrdenno35 hours1-11/+17
| * | shader: lower TLD and TLD4 with half-precision resultsrdenno35 hours1-0/+29
| * | shader: lower F2I from a half with a sign or high-half selectorrdenno35 hours1-3/+4
* | | shader: drop the slots of a failed handle subtree with its codeSssnowyyy29 hours1-4/+13
* | | shader: restore the handle build depth when a build throwsSssnowyyy29 hours1-4/+7
* | | shader: evaluate handle programs for image and texture buffer descriptorsSssnowyyy29 hours2-5/+38
* | | shader: tell handle-program textures apart when adding descriptorsSssnowyyy29 hours1-1/+6
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* | Merge nx2 into nx2-experimentalkraibse35 hours2-98/+387
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| * shader: keep root table reads the blit constants would zeroDuck91246 hours1-1/+11
| * video_core: keep root tables and bind table 0 as constant bank 17Duck91246 hours1-0/+21
| * shader: count only register writes in the callee link checkDuck91246 hours1-2/+7
| * shader: apply FSEL's floating operand modifiersDuck91246 hours1-1/+3
| * shader: lower more conversion, comparison and memory formsDuck91246 hours1-28/+66
| * shader: lower more 64-bit integer carry formsDuck91246 hours1-31/+171
| * shader: lower warp reductions, shared atomics and descriptor loadsDuck91246 hours1-15/+32
| * shader: lower more integer formsDuck91246 hours1-20/+127
| * shader: read extra texture descriptor buffers bindlessDuck91246 hours1-43/+108
* | Merge branch 'fix/nx2-hsetp2-register' into nx2-experimentalTakoroka42 hours1-3/+12
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| * | nx2: lower the HSETP2 register formTakoroka2 days1-3/+12
| * | Revert "nx2/ampere: implement ISBERD (0x923) and accept ISBEWR (0x927)"kraibse2 days1-30/+0
| * | Revert "Code review, cleanup and fix"kraibse2 days1-27/+22
| * | Code review, cleanup and fixnéo Luigi2 days1-22/+27
| * | nx2/ampere: implement ISBERD (0x923) and accept ISBEWR (0x927)Paulo Rossatto2 days1-0/+30
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* | nx2: lower the TXD and TXQ variants Splatoon Raiders uses latekraibse2 days1-1/+2
* | Merge commit 'e23b0f2fab9014225486beebd82fab8dbc0fe14c' into test/linux-all-p...Takoroka2 days1-12/+14
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| * | shader: keep the handle slot map thread-local instead of a pointer to itTakoroka2 days1-12/+14
* | | Merge remote-tracking branch 'origin/fix/nx2-storage-buffer-texture-handles' ...Takoroka2 days4-8/+552
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| * | shader: compute texture handles read from storage buffers for each drawTakoroka3 days3-6/+543
| * | nx2: drop R2UR's unreachable keep-old-value select when unpredicatedTakoroka3 days1-2/+9
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* | video_core: keep task/mesh pipelines out of the disk pipeline cacheTakoroka2 days1-1/+2
* | shader_recompiler: translate Switch 2 task and mesh programsTakoroka2 days30-8/+703
* | nx2: keep ISBERD/ISBEWR and lower UPOPC for task and mesh programsTakoroka2 days1-0/+23
* | nx2: lower TLD.SCR with a texel offsetTakoroka2 days1-2/+8
* | nx2: lower TLD4 with a texel offsetTakoroka2 days1-7/+16
* | nx2: lower ISETP.EX, the high half of 64-bit comparesTakoroka2 days1-1/+32
* | nx2: keep the uniform clamp before a jump table when instructions sit betweenTakoroka2 days1-4/+19
* | nx2: mirror uniform registers above UR27 below R216Takoroka2 days1-4/+21
* | nx2: lower TMML.BTakoroka2 days1-10/+14
* | nx2: lower TEX.B with an explicit LODTakoroka2 days1-4/+5
* | nx2: lower TLD4 with a uniform handleTakoroka2 days1-5/+17
* | nx2: lower TMML for 1D, 3D and cube textures and with a uniform handleTakoroka2 days1-14/+23
* | nx2: lower TLD.B at level zeroTakoroka2 days1-0/+33
* | nx2: lower TXQ.B and TXQ with three or four outputsTakoroka2 days1-10/+26
* | nx2: place TEX.B's handle after the coordinates; take .DC and .LZTakoroka2 days1-14/+19
* | nx2: lower IADD3.X with a register and a constant buffer operandTakoroka2 days1-2/+3
* | nx2: lower REDUX.MINTakoroka2 days1-6/+10
* | nx2: lower MATCH.ALL into P6Takoroka2 days1-7/+8
* | nx2: lower USHF on uniform registers above UR15Takoroka2 days1-14/+18
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