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path: root/src/video_core/engines/shader_bytecode.h
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* shader: Primitive Vulkan integrationReinUsesLisp2021-07-221-2298/+0
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* video_core: Remove unnecessary enum class casting in logging messagesLioncash2020-12-071-4/+2
| | | | | | | fmt now automatically prints the numeric value of an enum class member by default, so we don't need to use casts any more. Reduces the line noise a bit.
* shader_bytecode: Make use of [[nodiscard]] where applicableLioncash2020-11-201-73/+79
| | | | Ensures that all queried values are made use of.
* shader_bytecode: Eliminate variable shadowingLioncash2020-11-201-15/+17
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* shader/arithmetic: Implement FCMP immediate + register variantReinUsesLisp2020-10-281-0/+2
| | | | Trivially add the encoding for this.
* shader/half_set: Implement HSET2_IMMReinUsesLisp2020-06-221-0/+8
| | | | | | Add HSET2_IMM. Due to the complexity of the encoding avoid using BitField unions and read the relevant bits from the code itself. This is less error prone.
* shader_ir: Separate float-point comparisons in ordered and unorderedReinUsesLisp2020-05-091-12/+16
| | | | | This allows us to use native SPIR-V instructions without having to manually check for NAN.
* shader/arithmetic_integer: Implement IADD.XReinUsesLisp2020-04-251-0/+4
| | | | | IADD.X takes the carry flag and adds it to the result. This is generally used to emulate 64-bit operations with 32-bit registers.
* Merge pull request #3734 from ReinUsesLisp/half-float-modsbunnei2020-04-251-2/+0
|\ | | | | decode/arithmetic_half: Fix HADD2 and HMUL2 absolute and negation bits
| * decode/arithmetic_half: Fix HADD2 and HMUL2 absolute and negation bitsReinUsesLisp2020-04-231-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | The encoding for negation and absolute value was wrong. Extracting is now done manually. Similar instructions having different encodings is the rule, not the exception. To keep sanity and readability I preferred to extract the desired bit manually. This is implemented against nxas: https://github.com/ReinUsesLisp/nxas/blob/8dbc38995711cc12206aa370145a3a02665fd989/table.h#L68 That is itself tested against nvdisasm (Nvidia's official disassembler).
* | Fix -Wdeprecated-copy warning.Markus Wick2020-04-241-0/+1
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* CMakeLists: Specify -Wextra on linux buildsLioncash2020-04-151-1/+1
| | | | | | | | | | | Allows reporting more cases where logic errors may exist, such as implicit fallthrough cases, etc. We currently ignore unused parameters, since we currently have many cases where this is intentional (virtual interfaces). While we're at it, we can also tidy up any existing code that causes warnings. This also uncovered a few bugs as well.
* Merge pull request #3612 from ReinUsesLisp/redFernando Sahmkow2020-04-151-0/+8
|\ | | | | shader/memory: Implement RED.E.ADD and minor changes to ATOM
| * shader/memory: Implement RED.E.ADDReinUsesLisp2020-04-061-0/+8
| | | | | | | | | | | | | | | | Implements a reduction operation. It's an atomic operation that doesn't return a value. This commit introduces another primitive because some shading languages might have a primitive for reduction operations.
* | shader/arithmetic: Add FCMP_CR variantReinUsesLisp2020-04-141-2/+4
| | | | | | | | Adds another variant of FCMP.
* | Merge pull request #3578 from ReinUsesLisp/vmnmxFernando Sahmkow2020-04-121-1/+56
|\ \ | | | | | | shader/video: Partially implement VMNMX
| * | shader/video: Partially implement VMNMXReinUsesLisp2020-04-121-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implements the common usages for VMNMX. Inputs with a different size than 32 bits are not supported and sign mismatches aren't supported either. VMNMX works as follows: It grabs Ra and Rb and applies a maximum/minimum on them (this is defined by .MX), having in mind the input sign. This result can then be saturated. After the intermediate result is calculated, it applies another operation on it using Rc. These operations are merges, accumulations or another min/max pass. This instruction allows to implement with a more flexible approach GCN's min3 and max3 instructions (for instance).
| * | shader_bytecode: Fix I2I_IMM encodingReinUsesLisp2020-03-281-1/+1
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* | | shader_bytecode: Rename MOV_SYS to S2RReinUsesLisp2020-04-041-2/+2
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* | | shader_bytecode: Add encoding for BARReinUsesLisp2020-04-041-0/+2
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* | | shader_bytecode: Add encoding for VOTE.VTGReinUsesLisp2020-04-041-0/+2
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* | shader_decode: merge GlobalAtomicOp to AtomicOpnamkazy2020-03-301-13/+1
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* Merge pull request #3520 from ReinUsesLisp/legacy-varyingsbunnei2020-03-251-0/+6
|\ | | | | gl_shader_decompiler: Implement legacy varyings
| * shader/shader_ir: Track usage in input attribute and of legacy varyingsReinUsesLisp2020-03-151-0/+6
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* | shader_bytecode: update BFE instructions struct.Nguyen Dac Nam2020-03-131-8/+3
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* Merge pull request #3379 from ReinUsesLisp/cbuf-offsetbunnei2020-02-141-2/+2
|\ | | | | shader/decode: Fix constant buffer offsets
| * shader/decode: Fix constant buffer offsetsReinUsesLisp2020-02-051-2/+2
| | | | | | | | | | | | Some instances were using cbuf34.offset instead of cbuf34.GetOffset(). This returned the an invalid offset. Address those instances and rename offset to "shifted_offset" to avoid future bugs.
* | Merge pull request #3369 from ReinUsesLisp/shfbunnei2020-02-071-0/+20
|\ \ | |/ |/| shader/shift: Implement SHF
| * shader/shift: Implement SHF_LEFT_{IMM,R}ReinUsesLisp2020-02-011-0/+20
| | | | | | | | Shifts a pair of registers to the left and returns the high register.
* | Merge pull request #3357 from ReinUsesLisp/bfi-rcbunnei2020-02-041-0/+2
|\ \ | | | | | | shader/bfi: Implement register-constant buffer variant
| * | shader/bfi: Implement register-constant buffer variantReinUsesLisp2020-01-271-0/+2
| | | | | | | | | | | | | | | It's the same as the variant that was implemented, but it takes the operands from another source.
* | | Merge pull request #3356 from ReinUsesLisp/fcmpbunnei2020-02-041-0/+7
|\ \ \ | |_|/ |/| | shader/arithmetic: Implement FCMP
| * | shader/arithmetic: Implement FCMPReinUsesLisp2020-01-271-0/+7
| |/ | | | | | | | | Compares the third operand with zero, then selects between the first and second.
* / shader/memory: Implement ATOM.ADDReinUsesLisp2020-01-261-0/+30
|/ | | | | | | | | | | | | ATOM operates atomically on global memory. For now only add ATOM.ADD since that's what was found in commercial games. This asserts for ATOM.ADD.S32 (handling the others as unimplemented), although ATOM.ADD.U32 shouldn't be any different. This change forces us to change the default type on SPIR-V storage buffers from float to uint. We could also alias the buffers, but it's simpler for now to just use uint. While we are at it, abstract the code to avoid repetition.
* shader/memory: Implement ATOMS.ADD.U32ReinUsesLisp2020-01-161-3/+34
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* Merge pull request #3239 from ReinUsesLisp/p2rbunnei2019-12-311-1/+3
|\ | | | | shader/p2r: Implement P2R Pr
| * shader/r2p: Refactor P2R to support P2RReinUsesLisp2019-12-201-1/+3
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* | Merge pull request #3228 from ReinUsesLisp/ptpbunnei2019-12-261-6/+6
|\ \ | |/ |/| shader/texture: Implement AOFFI and PTP for TLD4 and TLD4S
| * shader/texture: Implement TLD4.PTPReinUsesLisp2019-12-161-6/+6
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* | shader_bytecode: Fix TLD4S encodingReinUsesLisp2019-12-171-1/+1
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* Shader_Ir: Correct TLD4S encoding and implement f16 flag.Fernando Sahmkow2019-12-111-1/+2
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* shader: Implement MEMBAR.GLReinUsesLisp2019-12-101-1/+17
| | | | Implement using memoryBarrier in GLSL and OpMemoryBarrier on SPIR-V.
* shader_ir/memory: Implement patch storesReinUsesLisp2019-12-091-1/+2
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* shader_bytecode: Remove corrupted characterReinUsesLisp2019-12-061-1/+1
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* Shader_IR: Implement TXD instruction.Fernando Sahmkow2019-11-141-0/+20
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* Shader_IR: Implement FLO instruction.Fernando Sahmkow2019-11-141-0/+6
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* Shader_Bytecode: Add encodings for FLO, SHF and TXDFernando Sahmkow2019-11-141-0/+18
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* Merge pull request #3081 from ReinUsesLisp/fswzadd-shufflesFernando Sahmkow2019-11-141-0/+10
|\ | | | | shader: Implement FSWZADD and reimplement SHFL
| * shader_ir/warp: Implement FSWZADDReinUsesLisp2019-11-071-0/+10
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* | video_core: Silence implicit conversion warningsReinUsesLisp2019-11-081-5/+7
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