diff options
| author | Takoroka <137927095+Takoroka@users.noreply.github.com> | 2026-10-30 11:57:47 -0400 |
|---|---|---|
| committer | Takoroka <137927095+Takoroka@users.noreply.github.com> | 2026-11-01 11:05:52 -0500 |
| commit | d88554cedb396863929dd31439dc8d4c92b367c8 (patch) | |
| tree | bc055b7e07c29223acfab5c71dc012fb1c7893c0 /src | |
| parent | 2f2b0a746832e94ea244062fdffa92102e9c5b6c (diff) | |
nx2: lower every ATOMS operation
Only ATOMS.ADD was lowered; Kirby Air Riders' compute shaders use
ATOMS.OR. The operation field (bits 87-90: ADD, MIN, MAX, INC, DEC, AND,
OR, XOR, EXCH) is numbered as Maxwell ATOMS' (bits 52-55) and bit 73 picks
S32 as Maxwell's type field does, so pass both through.
Diffstat (limited to 'src')
| -rw-r--r-- | src/shader_recompiler/frontend/ampere/lower_to_maxwell.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/shader_recompiler/frontend/ampere/lower_to_maxwell.h b/src/shader_recompiler/frontend/ampere/lower_to_maxwell.h index 9568951012..b59118efa3 100644 --- a/src/shader_recompiler/frontend/ampere/lower_to_maxwell.h +++ b/src/shader_recompiler/frontend/ampere/lower_to_maxwell.h @@ -899,12 +899,14 @@ inline LoweredProgram LowerToMaxwell(std::span<const Instruction> code) { (u64{offset >> 2} << 30)); break; } - case 0x38c: { // ATOMS.ADD.U32, naturally aligned shared byte offset. - const u32 offset = insn.Bits(40, 24); - if (insn.words[2] || (offset & 3)) return fail(index, "native shared atomic mode"); + case 0x38c: { // ATOMS (ADD/MIN/MAX/INC/DEC/AND/OR/XOR/EXCH, U32 or S32), aligned byte offset. + // The operation (bits 87-90) is numbered as in Maxwell ATOMS (52-55); bit 73 is S32. + const u32 offset = insn.Bits(40, 24), operation = insn.Bits(87, 4); + if ((insn.words[2] & ~0x07800200U) || operation > 8 || (offset & 3)) + return fail(index, "native shared atomic mode"); emit(0xec00000000000000ULL | predicate | dest | (u64{insn.Bits(24, 8)} << 8) | (u64{insn.Bits(32, 8)} << 20) | - (u64{offset >> 2} << 30)); + (u64{insn.Bits(73, 1)} << 28) | (u64{offset >> 2} << 30) | (u64{operation} << 52)); break; } case 0x3a8: { // ATOMG.E.ADD.STRONG.GPU U32 at a 64-bit register address plus an offset. |